為了簡化有限脈衝濾波器設計過程及產生一高效能低複雜度之濾波運算，本論文提出一高階合成輔助器。其中包括了各種濾波器最佳化設計方 式，IFIR，FRM，Multirate/Multistage。加上已熟知的快速濾波演算法的應用來進一步降低運算複雜度，並且加以延伸至較為一般性 的形式。在有限精確度設計下，差分編碼被應用來抵抗量化誤差，我們並且提出彈性精確度設計，特別針對串接式濾波器架構，可以有效降低硬體複雜度及達成有限 位元精確度下之高訊號及量化誤差比。最後，論文檢視了現階段實際應用的濾波器，應用於此高階合成軟體，並提出多項可行的設計分析以加速設計流程。

          In this thesis, for the simplification of FIR filter design and complexity reduction of a filtering process, we propose a high-level FIR filter synthesizer. This synthesizer combines many efficient filter design techniques including IFIR, FRM, and Multirate/Multistage techniques. In addition, the existing fast convolution algorithms are extended to more general forms and adopted for further complexity reduction. The differential coding scheme is utilized to reduce the dynamic range of the coefficients against the quantization error. Moreover, we proposed an efficient scheme for fixed-point cascaded-form FIR filter implementation, which is suitable for low-precision applications. Finally, the designs of several modern communication applications are automatically generated and compared with the conventional design approaches. The results show effectiveness of the proposed designs.

          Chapter 1 — Introduction                                  1
            1.1 Background                                          1
            1.2 Organization of the thesis                            3
          Chapter 2 — Filter design and optimization                5
            2.1 Basic filter design techniques                        5
            2.2 Filter optimization by Interpolated FIR technique    6
              2.2.1 IFIR design                                  6
              2.2.2 Computationally efficient IFIR Filters            8
            2.3 Filter design optimization-Frequency Response Masking 13
              2.3.1 FRM approach                                      13
              2.3.2 Filter design optimization — Frequency Response
            Masking — the optimum design                      18
              2.3.3 Complexity comparison between FRM and IFIR        20
              2.3.4 Half-band filter using FRM                        22
            2.4 Filter optimization — Multirate and Multistage      24
          Chapter 3 — Fast Filtering Algorithm                      27
            3.1 Fast Filtering Algorithm (BD)                        28
              3.1.1 The linear-phase BD algorithm                    32
            3.2 Jiang’s Fast Filtering algorithm                    32
            3.3 Jiang’s linear-phase algorithm                      34
              3.3.1 Type II/IV (4k)                                  35
              3.3.2 Type I/III (4k+1)                                36
              3.3.3 Type II/IV (4k+2)                                37
              3.3.4 Type I/III (4k+3)                                38
            3.4 Tsai’s Fast FIR Filtering algorithm                  42
              3.4.1 For Type II linear-phase filter                  43
            3.5 DSP code simulation results                          45
          Chapter 4 — Quantization Analysis and Implementation      49
            4.1 Modified DÉCOR                                        50
            4.2 Cascade-form structure implementation                53
          Chapter 5 — Simulation Results                            63
            5.1 Decimation filter design example                      65
            5.2 Filter design for IS-95 CDMA system                  73
              5.2.1 Filter design optimization                        73
              5.2.2 Quantization analysis                            77
          Chapter 6 — Conclusion                                    81
          References                                                  82

[1] R. Jain and P.T. Yang and T. Yoshino, “FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits,” IEEE Transactions on Signal Processing, Volume: 39 Issue: 7, Page(s): 1655 -1668, July 1991.
[2] E. Bidet and C. Joanblanq and P. Senn, “GENRIF: An Integrated VLSI FIR Filter Compiler,” European Conference [4th] on Design Automation, 1993, with the European Event in ASIC Design, Page(s): 466 -471, 22-25 Feb. 1993.
[3] J. Laskowski and H. Samueli, “A 150-Mhz 43-tap Half-band FIR Digital Filter in 1.2-μm CMOS Generated by Silicon Compiler,” Proceedings of the Custom Integrated Circuits Conference, Page(s): 11.4.1 -11.4.4, 3-6 May, 1992.
[4] Programs for Digital Signal Processing, IEEE Press, New York, 1979.
[5] A.V. Oppenheim and R.W. Schafer, Discrete-Time Signal Processing, Prentice-Hall, Englewood Cliffs, NJ, 1989.
[6] T. Neuvo and C.Y. Dong and S.K. Mitra, “Interpolated Finite Impulse Response Filters,” IEEE Transactions on Acoustics, Speech, and Signal Processing, Volume: 32 Issue: 3, Page(s): 563-570, Jun 1984.
[7] J.K. Kaiser, “Nonrecursive digital filter design using the  window function,” Digital Signal Processing II, New York: IEEE Press 1975.
[8] T. Saramäki and T. Neuvo and S.K. Mirta, “Design of Computationally Efficient Interpolated FIR Filters,” IEEE Transactions on Circuits and Systems, Volume: 35 Issue: 1, Page(s): 70 -88, Jan. 1988.
[9] Y.C. Lim, “Frequency Response Masking Approach for the Synthesis of sharp linear phase digital filters,” IEEE Transactions on Circuits and Systems, Volume: 33 Issue: 4, Page(s): 357 -364, Apr 1986.
[10] Y.C. Lim and Y. Lian, “The Optimum Design of One- and Two-Dimensional FIR Filters Using the Frequency Response Masking Technique,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume: 40 Issue: 2, Page(s): 88 -95, Feb. 1993.
[11] T. Saramäki and H. Johansson, “Optimization of FIR filters using the frequency-response masking approach,” The 2001 IEEE International Symposium on Circuits and Systems (ISCAS 2001), Volume: 2, Page(s): 177 -180, 6-9 May 2001.
[12] R. Yang and B. Liu and Y.C. Lim, “A new structure of sharp transition FIR Filters using Frequency-response-masking,” IEEE Transactions on Circuits and Systems, Volume: 35 Issue: 8, Page(s): 955 -966, Aug. 1988.
[13] T. Saramäki and J. Yli-Kaakinen, “Optimization of Frequency-response-masking based FIR filters with reduced complexity,” IEEE International Symposium on Circuits and Systems (ISCAS 2002), Volume: 3, Page(s): III-225 -III-228, 26-29 May 2002.
[14] T. Saramäki and Y.C. Lim and R. Yang, “The Synthesis of Half-band filter using Frequency-Response-Masking Technique,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume: 42 Issue: 1, Page(s): 58 -60, Jan 1995.
[15] R.E. Blahut, Fast Algorithms for Digital Signal Processings, Addision-Wesley, Reading, MA, 1985.
[16] Z.J. Mou and P. Duhamel, “Fast FIR Filtering: Algorithms and Implementations,” Signal Processing, Page(s): 377 -384, Dec 1987.
[17] A. Zergainoh and P. Duhamel, “Implementation and performance of composite fast FIR Filtering algorithm,” IEEE Workshop on VLSI Signal Processing, VIII, Page(s): 267 -276, 6-18 Sep. 1995.
[18] H.J. Nussbaumer, Fast Fourier Transform and Convolution Algorithms, Springer, Berlin/New York, 1981.
[19] 江瑞秋“低複雜度之濾波器掃描轉換”國立交通大學，碩士論文 , June 1999.
[20] S.G. Chen and R.J. Tsai, “A Novel Fast FIR Filtering algorithm and Its Implementation,” Proceedings of the EUIPCO-92, Belgium, Page(s): 945 -948, 1992.
[21] D. Li and J. Song and Y.C. Lim, “A Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients,” IEEE International Symposium on Circuits and Systems (ISCAS 1993), volume 1, Page(s): 84 -87, 3-6 May 1993.
[22] H. Samueli, “An Improved Search Algorithm for the Design of Multiplierless FIR Filters with Power-of-Two Coefficients,” IEEE Transactions on Circuits and Systems, Volume: 36 Issue: 7, Page(s): 1044 -1047, July 1989.
[23] I-Hsien Lee and Cheng-Shing Wu and An-Yen Wu, “Cost Efficient Multiplier-less filter structure based on modified DÉCOR transformation,” IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '01), Volume: 2, Page(s): 1065 -1068, 7-11 May 2001.
[24] K. Pahlavan and A.H. Levesque, Wireless Information Network, New York: Wesley, 1995.
[25] B. A. White and M.I. Elmasry, “Low-power design of decimation filters for a digital IF Receiver,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 8 Issue: 3, Page(s): 339 -345, June 2000.